1. Field
This disclosure relates to timer circuits, and, more particularly, to resistive-capacitive (RC) timer circuits.
2. Background Information
Advancements in silicon processing technologies employed to manufacture integrated circuits (ICs) may include, for example, reduction in circuit element sizes. Such reduction in circuit element sizes is one way the performance of such ICs may be improved and may be referred to as xe2x80x9cscaling.xe2x80x9d Those of skill in the art would be aware that current silicon processing technologies have circuit element dimensions, such as transistor sizes, which are smaller than 200 nano-meters (nm). Such processes are typically referred to as xe2x80x9csub-micronxe2x80x9d processes.
Such scaling, typically, has not had any significant adverse effects on the performance of most circuit designs, that is, circuit designs, historically, have typically required little modification to maintain functionality from one process generation to the next other than scaling such circuits in a corresponding manner with such process advancements. However, as further advancements are made in the area of sub-micron processes, the effects of such scaling, such as parasitics, for example, may become more pronounced. Parasitics, as they are typically referred to by those of skill in the art, in this context, may be defined as non-ideal, or intrinsic electrical characteristics of circuits embodied in such an IC. Such intrinsic characteristics may comprise, for example, capacitance, resistance and leakage currents. However, in future process generations, these factors may result in such circuits no longer working as intended by merely scaling the circuit elements in a manner corresponding with that process"" advancements. Therefore alternative embodiments of such circuits may be desired.